1. FIELD OF THE INVENTION
The present invention relates a to semiconductor memory device, such as a Dynamic Random Access Memory (DRAM), particularly to an output data latch circuit of the semiconductor memory device.
2. DESCRIPTION OF THE RELATED ART
A conventional semiconductor memory device employs a memory cell array having memory cells, respectively storing data therein, and associated peripheral circuits. In the peripheral circuits, there is an output data latch circuit to latch, in response to a latch timing control signal, a certain logic level of a data signal based upon data stored in one of the memory cells and to control, in response to an output timing control signal, a data output circuit so as to output signal having the certain logic level in every readout cycle defined by the external control signal such as RAS (Row Address Strobe) and CAS (Column Address Strobe) signals. The latch and output timing control signals, applied to the data latch circuit, can respectively be generated in prescribed limited timing by the conventional control signal generator comprised of conventional combination of logic circuits in response to the external control signal.